decoding circuit中文是什么意思

發音:

中文翻譯
造句

解碼電路
譯碼電路

decode vt. 譯碼；解碼；譯出指令。
circuit n. 1.(某一范圍的)周邊一圈；巡回，周游；巡回路線[ ...
colour decoding circuit 彩色解碼電路
decimal decoding circuit 十進制譯碼電路
station decoding circuit 站譯碼電路
decoding 解解碼; 解密; 譯出; 譯碼
adaptive decoding 自適應解碼; 自適應譯碼
algebraic decoding 代數解碼
analog decoding 模擬譯碼
block decoding 分組譯碼
board decoding 板譯碼
code decoding 譯碼, 電碼譯出, 電碼翻譯
coding decoding 編解碼
coincide decoding 重合譯碼; 重合擇碼
coincidence decoding 符合譯碼; 重合譯碼
color decoding 彩色解碼
decode，decoding 解碼
decoding action 譯碼作用
decoding algorithm 解碼算法; 譯碼算法
decoding and copying 譯繕
decoding assignment 解碼指定
decoding band 譯碼環
decoding bar 譯碼條
decoding capacitor 譯碼電容器
decoding complexity 譯碼復雜性

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例句與用法

The parallel form of the input sequence is decoded by means of a logical decoding circuit .
此并行形式序列通過邏輯解碼電路輸入。
An application of logic devices able to program to the decoding circuit
可編程邏輯器件在譯碼電路中的應用
Colour decoding circuit
彩色解碼電路
The results of p & r demonstrate that this design constructs a rs encoding / decoding circuit with a 3 . 2k internal fifo cache embedded , at the scale of 46k gates . its encoding and decoding speed are 66mhz and 47mhz respectively
布局布線后結果表明本文所設計的rs編碼器的速度可達到66mhz ；解碼速度可達到47mhz ，電路規模為4 . 6萬門，包含有3 . 2k的內部緩存fifo的rs編/解碼電路。
The hardware system includes power supply circuit , clock reset circuit , jtag model building circuit , decoding circuit , memory interface circuit , man - machine interface circuit and numeric control constant - current source interface circuit
硬件系統主要包括電源電路、時鐘復位電路、 jtag仿真接口電路，譯碼電路、存儲器接口電路、人機接口電路、 adc轉換電路和數控恒流源接口等。
Chapter two addresses in details systematic design and related modules of stand - alone door - lock system . the modules include mcu , recognition module , power , lcd , guide voice , i / o decoding circuit , rtc , unlock circuit , power save and anti - interference design
第二部分著重介紹了指紋門禁單機系統的系統總體設計以及系統中涉及到的各模塊的基礎知識、設計思路和具體實現。
In this paper we discuss mca circuit , the sequential logic for mca data collection , for the setting of the uld , lld and the gain of pga , as well as the combinational logic for decoding circuits of the computer interface , based on cpld
本文詳細論述了利用cpld實現的脈沖幅度多道電路及其數據采集的時序控制邏輯、閾值設定和程控放大倍數設定的時序控制邏四川大學碩士學位論文輯、以及與計算機接口的譯碼電路等組合控制邏輯。
The application of hardware decoding circuit is widely , because it not only can be used on computer , but also can be used on consumer equipment like digital - tv and dvd - player . the avs and h . 264 standards and the architecture of digital video decoder chip are investigated in the thesis , and a high - definition multi - mode decoder soc chip is proposed . the chip can support avs level 4 . 0 / 6 . 0 and h . 264 main profile level 4 . 0
本文在研究了avs和h . 264視頻編碼標準和數字視頻解碼芯片系統結構的基礎上,設計了同時支持avs和h . 264的高清解碼soc芯片,能夠對avslevel4 . 0 / 6 . 0和h . 264mainprofilelevel4 . 0的高清晰度視頻碼流實時解碼。
It emphatically describes address decoding circuit and controling circuit of fpga in hardware , and describes dma transmission mode and disposing of the interrupt in driver , and describes how to get data from wav file , and how to organize data before transmition , and how to chose appropriate quantity of data transmition every time in application
著重闡述了硬件設計中fpga內部重要的譯碼及控制電路設計,驅動程序中dma ( directmemoryaccess )的傳輸及中斷處理,應用程序中對于兩個聲音文件數據的正確獲取、組合及分割等問題。
There are several aspects of work that was done in this thesis mainly . firstly , the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed . secondly , decoding circuit of the under - water long - range remote control system was designed with fpga , including vhdl coding , simulation , synthesis , place & route , etc . besides , power consumption to fpga that is designed is estimated in this thesis . lastly , we designed and made one pcb to verify and test fpga decoding chip that is designed , and debugged and tested it finally
首先，深入研究和分析了在頻域實現水下遠程遙控解碼的原理并進行了遙控指令編碼設計；其次，用altera公司的cyclone系列fpga芯片完成了水下遠程遙控fpga解碼芯片的設計工作，包括硬件描述語言( vhdl )編碼、電路前后仿真、綜合和布局布線工作，并對設計的fpga解碼芯片進行了初步的功耗估算；最后設計制作了一塊fpga解碼芯片電路驗證測試板，并完成了電路調試和測試。

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